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never stop thinking. hys64d64020hbdl?5?c hys64d64020gbdl?5?c hys64d64020hbdl?6?c hys64d64020gbdl?6?c 200-pin small outline dual-in-line memory modules so-dimm ddr sdram data sheet, rev. 1.11, dec. 2004 memory products
edition 2004-12 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain co mponents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology , delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safe ty or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys64d64020hbdl?5?c hys64d64020gbdl?5?c hys64d64020hbdl?6?c hys64d64020gbdl?6?c 200-pin small outline dual-in-line memory modules so-dimm ddr sdram data sheet, rev. 1.11, dec. 2004 memory products
template: mp_a4_v2.0_2003-06-06.fm hys64d64020hbdl?5?c, hys64d 64020gbdl?5?c, hys64d64020hbdl ?6?c,hys64d64020gbdl?6?c revision history: rev. 1.11 2004-12 previous version: rev. 1.1 2004-05 page subjects (major changes since last revision) all 6 , 18 change t rap to equal t rcd 26 change package outline drawing we listen to your comments any information within this do cument that you feel is wro ng, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
data sheet 5 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 current specification and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 spd contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table of contents
data sheet 6 rev. 1.11, 2004-12 200-pin small outline dual -in-line memory modules so-dimm hys64d64020hbdl?5?c hys64d64020gbdl?5?c hys64d64020hbdl?6?c hys64d64020gbdl?6?c 1overview 1.1 features ? non-parity 200-pin small outline dual-in-line memory modules ? two ranks 64m 64 organization ? jedec standard double data ra te synchronous drams (ddr sdram) ?single +2.5v ( 0.2 v) power supply and single +2.6v ( 0.1 v) power supply for ddr400 ? built with 256 mbit ddr sdrams organised as 8 in p?tfbga?60 packages ? programmable cas latency, burst length, and wrap sequence (sequential & interleave) ? auto refresh (cbr) and self refresh ? ras-lockout supported t rap = t rcd ? all inputs and outputs sstl_2 compatible ? serial presence detect with e 2 prom ? jedec standard form factor: 67.60 mm 31.75 mm 3.80 mm ? gold plated contacts table 1 performance 1.2 description the hys64d64020hbdl?5?c and hys64d64020gbdl?5?c are industry standard 200-pin small outline dual-in-line memory modules (so-dimms) organized as 64m 64. the memory array is designed with double data rate synchronous drams (ddr s dram). a variety of decoupling capaci tors are mounted on the pc board. the dimms feature serial presenc e detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. part number speed code ?5 ? 6unit speed grade component ddr400b ddr333b ? module pc3200?3033 pc2700?2533 ? max. clock frequency @cl3 f ck3 200 166 mhz @cl2.5 f ck2.5 166 166 mhz @cl2 f ck2 133 133 mhz
data sheet 7 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules overview notes 1. all part numbers end with a place c ode designating the silicon-die revisi on. reference information available on request. example: hys64d32020gdl-6-b, indicating rev. b dies are used for sdram components. 2. the compliance code is printed on the module labels de scribing the speed sort (for example ?pc2700?), the latencies and spd code definition (for example ?2033 ? 0? means cas latency of 2.0 clocks, rcd 1) latency of 3 clocks, row precharge latency of 3 clocks, and jede c spd code definiton vers ion 0), and the raw card used for this module. table 2 ordering information type compliance code description sdram technology pc3200 (cl=3.0) hys64d64020gbdl?5?c pc3200s?3033?1?z two ranks 512 mb so-dimm 32 mbit ( 8) pc2700 (cl=2.5) hys64d64020gbdl?6?c pc2700s?2533?0?z two ranks 512 mb so-dimm 32 mbit ( 8) pc3200 (cl=3.0) hys64d64020hbdl?5?c pc3200s?3033?1?z two ranks 512 mb so-dimm 32 mbit ( 8) pc2700 (cl=2.5) hys64d64020hbdl?6?c pc2700s?2533?0?z two ranks 512 mb so-dimm 32 mbit ( 8) 1) rcd: row-column-delay
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 8 rev. 1.11, 2004-12 08252003-0rwi-czgz 2 pin configuration the pin configuration of the unbuffered small outline ddr sdram dimm is listed by function in table 3 (184 pins). the abbreviations used in columns pin and buffer type are explained in table 4 and table 5 respectively. the pin numbering is depicted in figure 1 . table 3 pin configuration of so-dimm pin# name pin type buffer type function clock signals 35 ck0 i sstl clock signal 160 ck1 i sstl clock signal 89 ck2 i sstl clock signal note: ecc type module nc nc ? note: non-ecc type module 37 ck0 isstl complement clock 158 ck1 isstl complement clock 91 ck2 isstl complement clock note: ecc type module nc nc ? note: non-ecc type module 96 cke0 i sstl clock enable rank 0 95 cke1 i sstl clock enable rank 1 note: 2-rank module nc nc ? note: 1-rank module control signals 121 s0 isstl chip select rank 0 122 s1 isstl chip select rank 1 note: 2-ranks module nc nc ? note: 1-rank module 118 ras isstl row address strobe 120 cas isstl column address strobe 119 we isstl write enable address signals 117 ba0 i sstl bank address bus 1:0 116 ba1 i sstl 112 a0 i sstl address bus 11:0 111 a1 i sstl 110 a2 i sstl 109 a3 i sstl 108 a4 i sstl 107 a5 i sstl 106 a6 i sstl 105 a7 i sstl 102 a8 i sstl 101 a9 i sstl 115 a10 i sstl ap i sstl 100 a11 i sstl 99 a12 i sstl address signal 12 note: module based on 256 mbit or larger dies nc nc ? note: 128 mbit based module 123 a13 i sstl address signal 13 note: 1 gbit based module nc nc ? note: module based on 512 mbit or smaller dies data signals 5dq0i/osstl data bus 63:0 7dq1i/osstl 13 dq2 i/o sstl 17 dq3 i/o sstl 6dq4i/osstl 8dq5i/osstl 14 dq6 i/o sstl 18 dq7 i/o sstl 19 dq8 i/o sstl 23 dq9 i/o sstl 29 dq10 i/o sstl 31 dq11 i/o sstl 20 dq12 i/o sstl 24 dq13 i/o sstl table 3 pin configur ation of so-dimm (cont?d) pin# name pin type buffer type function
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 9 rev. 1.11, 2004-12 08252003-0rwi-czgz 30 dq14 i/o sstl data bus 63:0 32 dq15 i/o sstl 41 dq16 i/o sstl 43 dq17 i/o sstl 49 dq18 i/o sstl 53 dq19 i/o sstl 42 dq20 i/o sstl 44 dq21 i/o sstl 50 dq22 i/o sstl 54 dq23 i/o sstl 55 dq24 i/o sstl 59 dq25 i/o sstl 65 dq26 i/o sstl 67 dq27 i/o sstl 56 dq28 i/o sstl 60 dq29 i/o sstl 66 dq30 i/o sstl 68 dq31 i/o sstl 127 dq32 i/o sstl 129 dq33 i/o sstl 135 dq34 i/o sstl 139 dq35 i/o sstl 128 dq36 i/o sstl 130 dq37 i/o sstl 136 dq38 i/o sstl 140 dq39 i/o sstl 141 dq40 i/o sstl 145 dq41 i/o sstl 151 dq42 i/o sstl 153 dq43 i/o sstl 142 dq44 i/o sstl 146 dq45 i/o sstl 152 dq46 i/o sstl 154 dq47 i/o sstl 163 dq48 i/o sstl 165 dq49 i/o sstl 171 dq50 i/o sstl 175 dq51 i/o sstl 164 dq52 i/o sstl 166 dq53 i/o sstl table 3 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function 172 dq54 i/o sstl data bus 63:0 176 dq55 i/o sstl 177 dq56 i/o sstl 181 dq57 i/o sstl 187 dq58 i/o sstl 189 dq59 i/o sstl 178 dq60 i/o sstl 182 dq61 i/o sstl 188 dq62 i/o sstl 190 dq63 i/o sstl 71 cb0 i/o sstl check bit 0 note: ecc type module nc nc ? note: non-ecc module 73 cb1 i/o sstl check bit 1 note: ecc type module nc nc ? note: non-ecc module 79 cb2 i/o sstl check bit 2 note: ecc type module nc nc ? note: non-ecc module 83 cb3 i/o sstl check bit 3 note: ecc type module nc nc ? note: non-ecc module 72 cb4 i/o sstl check bit 4 note: ecc type module nc nc ? note: non-ecc module 74 cb5 i/o sstl check bit 5 note: ecc type module nc nc ? note: non-ecc module table 3 pin configur ation of so-dimm (cont?d) pin# name pin type buffer type function
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 10 rev. 1.11, 2004-12 08252003-0rwi-czgz 80 cb6 i/o sstl check bit 6 note: ecc type module nc nc ? note: non-ecc module 84 cb7 i/o sstl check bit 7 note: ecc type module nc nc ? note: non-ecc module 11 dqs0 i/o sstl data strobes 7:0 note: see block diagram for corresponding dq signals 25 dqs1 i/o sstl 47 dqs2 i/o sstl 61 dqs3 i/o sstl 133 dqs4 i/o sstl 147 dqs5 i/o sstl 169 dqs6 i/o sstl 183 dqs7 i/o sstl 77 dqs8 i/o sstl data strobe 8 note: ecc type module nc nc ? note: non-ecc module 12 dm0 i sstl data mask 7:0 26 dm1 i sstl 48 dm2 i sstl 62 dm3 i sstl 134 dm4 i sstl 148 dm5 i sstl 170 dm6 i sstl 184 dm7 i sstl 78 dm8 i sstl data mask 8 note: ecc type module nc nc ? note: non-ecc module eeprom 195 scl i cmos serial bus clock 193 sda i/o od serial bus data 194 sa0 i cmos slave address select bus 2:0 196 sa1 i cmos 198 sa2 i cmos table 3 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function power supplies 1,2 v ref ai ? i/o reference voltage 197 v ddspd pwr ? eeprom power supply 9,10, 21, 22, 33, 34, 36, 45, 46, 57, 58, 69, 70, 81, 82, 92, 93, 94, 113, 114, 131, 132, 143, 144, 155, 156, 157, 167, 168, 179, 180, 191, 192 v dd pwr ? power supply table 3 pin configur ation of so-dimm (cont?d) pin# name pin type buffer type function
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 11 rev. 1.11, 2004-12 08252003-0rwi-czgz 3,4, 15, 16, 27, 28, 38, 39, 40, 51, 52, 63, 64, 75, 76, 87, 88, 90, 103, 104, 125, 126, 137, 138, 149, 150, 159, 161, 162, 173, 174, 185, 186 v ss gnd ? ground plane other pins 199 v ddid ood v dd identification note: pin in tristate, indicating v dd and v ddq nets connected on pcb table 3 pin configuration of so-dimm (cont?d) pin# name pin type buffer type function 85, 86, 97, 98, 124, 200 nc nc ? not connected note: pins not connected on infineon so dimms table 4 abbreviations for pin type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 5 abbreviations for buffer type abbreviation description sstl serial stub terminalted logic (sstl2) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or. table 3 pin configur ation of so-dimm (cont?d) pin# name pin type buffer type function
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 12 rev. 1.11, 2004-12 08252003-0rwi-czgz figure 1 pin configuration diagram 200-pin so-dimm table 6 address format density organization memory ranks sdrams # of sdrams # of row/bank/ columns bits refresh period interval 512mb 64m 64 2 32m 8 16 13/2/10 8k 64 ms 7.8 s mppd0040 pin 002 pin 006 pin 010 pin 014 pin 018 pin 022 pin 026 pin 030 pin 034 pin 038 - - - - - - - - - - pin 004 pin 008 pin 012 pin 016 pin 020 pin 024 pin 028 pin 032 pin 036 pin 040 - - - - - - - - - - v ref dq4 v dd dq6 dq7 v dd dm1 dq14 v dd dq6 dm0 dq12 dq13 dq15 pin 044 pin 048 pin 052 pin 056 pin 060 pin 064 pin 068 pin 072 pin 076 pin 080 pin 084 pin 088 pin 092 pin 096 pin 100 pin 104 pin 108 pin 112 pin 116 pin 120 pin 124 pin 128 pin 132 pin 136 pin 140 pin 144 pin 148 pin 152 pin 156 pin 160 pin 164 pin 168 pin 172 pin 176 pin 180 pin 184 pin 188 pin 192 pin 196 pin 200 dq21 dm2 dq28 dq29 dq31 cb4/nc cb6/nc cb7/nc cke0 a11 a4 a0 ba1 cas nc dq36 dq38 dq39 dm5 dq46 ck1 dq52 dq54 dq55 dm7 dq62 sa1 nc - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 042 pin 046 pin 050 pin 054 pin 058 pin 062 pin 066 pin 070 pin 074 pin 078 pin 082 pin 086 pin 090 pin 094 pin 098 pin 102 pin 106 pin 110 pin 114 pin 118 pin 122 pin 126 pin 130 pin 134 pin 138 pin 142 pin 146 pin 150 pin 154 pin 158 pin 162 pin 166 pin 170 pin 174 pin 178 pin 182 pin 186 pin 190 pin 194 pin 198 dq20 dq22 dq23 v dd dm3 dq30 cb5/nc dm8/nc v dd nc v ss v dd nc a8 a6 a2 v dd ras s1/nc dq37 dm4 dq44 dq45 dq47 ck1 dq53 dm6 dq60 dq61 v ss dq63 sa0 sa2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 001 pin 005 pin 009 pin 013 pin 017 pin 021 pin 025 pin 029 pin 033 pin 037 - - - - - - - - - - pin 003 pin 007 pin 011 pin 015 pin 019 pin 023 pin 027 pin 031 pin 035 pin 039 - - - - - - - - - - v ref dq0 v dd dq2 dq3 v dd dqs1 dq10 v dd ck0 dq1 dqs0 dq8 dq09 dq11 ck0 pin 043 pin 047 pin 051 pin 055 pin 059 pin 063 pin 067 pin 071 pin 075 pin 079 pin 083 pin 087 pin 091 pin 095 pin 099 pin 103 pin 107 pin 111 pin 115 pin 119 pin 123 pin 127 pin 131 pin 135 pin 139 pin 143 pin 147 pin 151 pin 155 pin 159 pin 163 pin 167 pin 171 pin 175 pin 179 pin 183 pin 187 pin 191 pin 195 pin 199 dq17 dqs2 dq33 dq25 dq27 cb0/nc cb2/nc cb3/nc ck2/nc cke1/nc a12/nc a5 a1 a10/ap we a13/nc dq32 dq34 dq35 dqs5 dq42 dq48 dq50 dq51 dqs7 dq58 scl v ddid - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 041 pin 045 pin 049 pin 053 pin 057 pin 061 pin 065 pin 069 pin 073 pin 077 pin 081 pin 085 pin 089 pin 093 pin 097 pin 101 pin 105 pin 109 pin 113 pin 117 pin 121 pin 125 pin 129 pin 133 pin 137 pin 141 pin 145 pin 149 pin 153 pin 157 pin 161 pin 165 pin 169 pin 173 pin 177 pin 181 pin 185 pin 189 pin 193 pin 197 dq16 v dd dq18 dq19 v dd dqs3 dq26 v dd cb1/nc dqs8/nc v dd nc ck2/nc v dd nc a9 a7 a3 v dd ba0 s0 dq33 dqs4 dq40 dq41 dq43 v dd dq49 dqs6 dq56 dq57 v ss dq59 sda v ddspd - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - v dd v dd v dd v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss frontside backside v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v ss v dd
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules pin configuration data sheet 13 rev. 1.11, 2004-12 08252003-0rwi-czgz figure 2 block diagram so-dimm raw card a ( 64, 2 ranks, 8) note: 1. v dd = v ddq , therefore v ddid strap open 2. dq, dqs, dm resistors are 22 ? 5%

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$ $ % & % ' ' & % ' ' table 7 clock signal loads clock input number of sdrams note ck0, ck0 8 sdrams ? ck1, ck1 8 sdrams ? ck2, ck2 0 sdrams ?
data sheet 14 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics 3 electrical characteristics 3.1 operating conditions attention: permanent damage to the device may occu r if ?absolute maximum ratings? are exceeded. this is a stress rating only, and functional operati on should be restricted to recommended operation conditions. exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. table 8 absolute maximum ratings parameter symbol values unit note/ test condition min. typ. max. voltage on i/o pins relative to v ss v in , v out ?0.5 ? v ddq + 0.5 v? voltage on inputs relative to v ss v in ?1 ? +3.6 v ? voltage on v dd supply relative to v ss v dd ?1 ? +3.6 v ? voltage on v ddq supply relative to v ss v ddq ?1 ? +3.6 v ? operating temperature (ambient) t a 0?+70 c? storage temperature (plastic) t stg -55 ? +150 c? power dissipation (per sdram component) p d ?1?w? short circuit output current i out ?50?ma? table 9 electrical characteristics and dc operating conditions parameter symbol values unit note/test condition 1) min. typ. max. device supply voltage v dd 2.3 2.5 2.7 v f ck 166 mhz device supply voltage v dd 2.5 2.6 2.7 v f ck >166mhz 2) output supply voltage v ddq 2.3 2.5 2.7 v f ck 166 mhz 3) output supply voltage v ddq 2.5 2.6 2.7 v f ck >166mhz 2)3) eeprom supply voltage v ddspd 2.3 2.5 3.6 v ? supply voltage, i/o supply voltage v ss , v ssq 00v? input reference voltage v ref 0.49 v ddq 0.5 v ddq 0.51 v ddq v 4) i/o termination voltage (system) v tt v ref ? 0.04 v ref + 0.04 v 5) input high (logic1) voltage v ih(dc) v ref + 0.15 v ddq + 0.3 v 6) input low (logic0) voltage v il(dc) ?0.3 v ref ? 0.15 v 6) input voltage level, ck and ck inputs v in(dc) ?0.3 v ddq + 0.3 v 6) input differential voltage, ck and ck inputs v id(dc) 0.36 v ddq + 0.6 v 6)7) vi-matching pull-up current to pull-down current vi ratio 0.71 1.4 ? 8)
data sheet 15 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics input leakage current i i ?2 2 a any input 0 v v in v dd ; all other pins not under test =0v 9) output leakage current i oz ?5 5 a dqs are disabled; 0v v out v ddq 9) output high current, normal strength driver i oh ? ?16.2 ma v out = 1.95 v output low current, normal strength driver i ol 16.2 ? ma v out = 0.35 v 1) 0 c t a 70 c; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v; v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400); 2) ddr400 conditions apply for all clock frequencies above 166 mhz 3) under all conditions, v ddq must be less than or equal to v dd . 4) peak to peak ac noise on v ref may not exceed 2% v ref (dc) . v ref is also expected to track noise variations in v ddq . 5) v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref , and must track variations in the dc level of v ref . 6) inputs are not recognized as valid until v ref stabilizes. 7) v id is the magnitude of the differ ence between the input level on ck and the input level on ck . 8) the ratio of the pull-up current to the pull-down current is specified for the sa me temperature and volt age, over the entire temperature and voltage range, for device drain to source volt age from 0.25 to 1.0 v. for a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 9) values are shown per pin. table 9 electrical characteristics and dc operating conditions (cont?d) parameter symbol values unit note/test condition 1) min. typ. max.
data sheet 16 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics 3.2 current specifi cation and conditions table 10 i dd conditions parameter symbol operating current 0 one bank; active/ precharge; dq, dm, and dq s inputs changing once per clock cycle; address and control inputs chan ging once every two clock cycles. i dd0 operating current 1 one bank; active/read/precharge; burst length = 4; see component data sheet. i dd1 precharge power-down standby current all banks idle; powe r-down mode; cke v il,max i dd2p precharge floating standby current cs v ih,,min , all banks idle; cke v ih,min ; address and other control inputs changing once per clock cycle; v in = v ref for dq, dqs and dm. i dd2f precharge quiet standby current cs v ihmin , all banks idle; cke v ih,min ; v in = v ref for dq, dqs and dm; address and other control inputs stable at v ih,min or v il,max . i dd2q active power-down standby current one bank active; power-down mode; cke v ilmax ; v in = v ref for dq, dqs and dm. i dd3p active standby current one bank active; cs v ih,min ; cke v ih,min ; t rc = t ras,max ; dq, dm and dqs inputs changing twice per clock cycle; address and control inputs c hanging once per clock cycle. i dd3n operating current read one bank active; burst length = 2; reads; continuous burst; address and control inputs c hanging once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b; i out =0ma i dd4r operating current write one bank active; burst length = 2; writes; continuous burst; address and control inputs c hanging once per clock cycle; 50% of data outputs changing on every clock edge; cl = 2 for ddr266(a), cl = 3 for ddr333 and ddr400b i dd4w auto-refresh current t rc = t rfcmin , burst refresh i dd5 self-refresh current cke 0.2 v; external clock on i dd6 operating current 7 four bank interleaving with burst length = 4; see component data sheet. i dd7
data sheet 17 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics table 11 i dd specification for hys64d64020[g/h]bdl?5?c product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition fo r maximum values: v dd =2.7v, t a =10c organization 512mb 64 2 ranks ?5 symbol typ. max. i dd0 940 1150 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of component s of rank 1 and 2; n =0 for 1 rank modules i dd1 1100 1310 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 480 580 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 320 450 ma 5) i dd2q 210 290 ma 5) i dd3p 610 720 ma 5) i dd3n 690 860 ma 5) i dd4r 1140 1390 ma 3)4) i dd4w 1140 1470 ma 3) i dd5 360 450 ma 3) i dd6 16 17.6 ma 5) i dd7 2020 2430 ma 3)4)
data sheet 18 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics table 12 i dd specification for hys64d64020[g/h]bdl?6?c product type hys64d64020gbdl?6-?c hys64d64020hbdl?6?c unit note 1)2) 1) module i dd values are calculated on the basis of component i dd and can be measured differently according to dq loading capacity. 2) test condition fo r maximum values: v dd =2.7v, t a =10c organization 512mb 64 2 ranks ?6 symbol typ. max. i dd0 810 960 ma 3) 3) the module i ddx values are calculated from the i ddx values of the component data sheet as follows: m i ddx [component] + n i dd3n [component] with m and n number of component s of rank 1 and 2; n =0 for 1 rank modules i dd1 930 1120 ma 3)4) 4) dq i/o ( i ddq ) currents are not included in the calculations (see note 1) i dd2p 400 480 ma 5) 5) the module i ddx values are calculated from the corrponent i ddx data sheet values as: ( m + n ) i ddx [component] i dd2f 270 380 ma 5) i dd2q 180 240 ma 5) i dd3p 510 610 ma 5) i dd3n 580 720 ma 5) i dd4r 970 1160 ma 3)4) i dd4w 1010 1240 ma 3) i dd5 300 380 ma 3) i dd6 16 17.6 ma 5) i dd7 1730 2080 ma 3)4) table 13 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max. dq output access time from ck/ck t ac ?0.5 +0.5 ?0.7 +0.7 ns 2)3)4)5) ck high-level width t ch 0.45 0.55 0.45 0.55 t ck 2)3)4)5) clock cycle time t ck 5 8 6 12 ns cl = 3.0 2)3)4)5) 6 12 6 12 ns cl = 2.5 2)3)4)5) 7.5 12 7.5 12 ns cl = 2.0 2)3)4)5) ck low-level width t cl 0.45 0.55 0.45 0.55 t ck 2)3)4)5)
data sheet 19 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics auto precharge write recovery + precharge time t dal ( t wr / t ck )+( t rp / t ck ) t ck 2)3)4)5)6) dq and dm input hold time t dh 0.4 ? 0.45 ? ns 2)3)4)5) dq and dm input pulse width (each input) t dipw 1.75 ? 1.75 ? ns 2)3)4)5)6) dqs output access time from ck/ck t dqsck ?0.6 +0.6 ?0.6 +0.6 ns 2)3)4)5) dqs input low (high) pulse width (write cycle) t dqsl,h 0.35 ? 0.35 ? t ck 2)3)4)5) dqs-dq skew (dqs and associated dq signals) t dqsq ? +0.40 ? +0.40 ns tfbga 2)3)4)5) write command to 1 st dqs latching transition t dqss 0.72 1.25 0.75 1.25 t ck 2)3)4)5) dq and dm input setup time t ds 0.4 ? 0.45 ? ns 2)3)4)5) dqs falling edge hold time from ck (write cycle) t dsh 0.2 ? 0.2 ? t ck 2)3)4)5) dqs falling edge to ck setup time (write cycle) t dss 0.2 ? 0.2 ? t ck 2)3)4)5) clock half period t hp min. ( t cl , t ch )min. ( t cl , t ch )ns 2)3)4)5) data-out high-impedance time from ck/ck t hz ? +0.7 ?0.7 +0.7 ns 2)3)4)5)7) address and control input hold time t ih 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) control and addr. input pulse width (each input) t ipw 2.2 ? 2.2 ? ns 2)3)4)5)9) address and control input setup time t is 0.6 ? 0.75 ? ns fast slew rate 3)4)5)6)8) 0.7 ? 0.8 ? ns slow slew rate 3)4)5)6)8) data-out low-impedance time from ck/ck t lz ?0.7 +0.7 ?0.7 +0.7 ns 2)3)4)5)7) mode register set command cycle time t mrd 2?2? t ck 2)3)4)5) dq/dqs output hold time t qh t hp ? t qhs t hp ? t qhs ns 2)3)4)5) data hold skew factor t qhs ? +0.50 ? +0.50 ns tfbga 2)3)4)5) active to autoprecharge delay t rap t rcd ? t rcd ?ns 2)3)4)5) active to precharge command t ras 40 70e+3 42 70e+3 ns 2)3)4)5) active to active/auto-refresh command period t rc 55 ? 60 ? ns 2)3)4)5) active to read or write delay t rcd 15 ? 18 ? ns 2)3)4)5) table 13 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
data sheet 20 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules electrical characteristics average periodic refresh interval t refi ? 7.8 ? 7.8 s 2)3)4)5)10) auto-refresh to active/auto- refresh command period t rfc 70 ? 72 ? ns 2)3)4)5) precharge command period t rp 15 ? 18 ? ns 2)3)4)5) read preamble t rpre 0.9 1.1 0.9 1.1 t ck 2)3)4)5) read postamble t rpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5) active bank a to active bank b command t rrd 10 ? 12 ? ns 2)3)4)5) write preamble t wpre 0.25 ? 0.25 ? t ck 2)3)4)5) write preamble setup time t wpres 0?0?ns 2)3)4)5)11) write postamble t wpst 0.40 0.60 0.40 0.60 t ck 2)3)4)5)12) write recovery time t wr 15 ? 15 ? ns 2)3)4)5) internal write to read command delay t wtr 2?1? t ck 2)3)4)5) exit self-refresh to non-read command t xsnr 75 ? 75 ? ns 2)3)4)5) exit self-refresh to read command t xsrd 200 ? 200 ? t ck 2)3)4)5) 1) 0 c t a 70 c ; v ddq = 2.5 v 0.2 v, v dd = +2.5 v 0.2 v (ddr333); v ddq = 2.6 v 0.1 v, v dd = +2.6 v 0.1 v (ddr400) 2) input slew rate 1 v/ns for ddr400, ddr333 3) the ck/ck input reference level (for timing reference to ck/ck ) is the point at which ck and ck cross: the input reference level for signals other than ck/ck , is v ref . ck/ck slew rate are 1.0 v/ns. 4) inputs are not recognized as valid until v ref stabilizes. 5) the output timing reference level, as measured at the timing reference point indicated in ac characteristics (note 3) is v tt . 6) for each of the terms, if not already an integer, round to the ne xt highest integer. t ck is equal to the actual system clock cycle time. 7) t hz and t lz transitions occur in the same access time windows as valid data transitions. these parameters are not referred to a specific voltage level, but sp ecify when the device is no longer driv ing (hz), or begins driving (lz). 8) fast slew rate 1.0 v/ns , slow slew rate 0.5 v/ns and < 1 v/ns for command/address and ck & ck slew rate > 1.0 v/ ns, measured between v ih(ac) and v il(ac) . 9) these parameters guarantee device timing, but they are not necessarily tested on each device. 10) a maximum of eight autorefresh commands can be posted to any given ddr sdram device. 11) the specific requirement is th at dqs be valid (high,low, or some point on a valid transition) on or before this ck edge. a valid transition is defined as monotonic and meeting the input slew rate specificat ionsof the device. when no writes were previously in progress on the bus, dqs will be transitioning fr om hi-z to logic low. if a previous write was in progress, dqs could be high, low at this time, depending on t dqss . 12) the maximum limit for this parameter is not a device limit. the device operates with a greater value for th is parameter, but system performance (bus turnar ound) degrades accordingly. table 13 ac timing - absolute specifications for pc3200 and pc2700 parameter symbol ?5 ?6 unit note/ test condition 1) ddr400b ddr333 min. max. min. max.
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules spd contents data sheet 21 rev. 1.11, 2004-12 4spdcontents table 14 spd codes for hys64d64020hbdl?5?c and hys64d64020gbdl?5?c product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512 mb 512 mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?3033?1 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex 0 programmed spd bytes in e2prom 80 80 1 total number of bytes in e2prom 08 08 2 memory type (ddr = 07h) 07 07 3 number of row addresses 0d 0d 4 number of column addresses 0a 0a 5 number of dimm ranks 02 02 6 data width (lsb) 40 40 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 t ck @ cl max (byte 18) [ns] 50 50 10 t ac sdram @ cl max (byte 18) [ns] 50 50 11 error correction support 00 00 12 refresh rate 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 00 15 t ccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram device 04 04 18 cas latency 1c 1c 19 cs latency 01 01 20 write latency 02 02 21 dimm attributes 20 20 22 component attributes c1 c1 23 t ck @ cl max -0.5 (byte 18) [ns] 60 60 24 t ac sdram @ cl max -0.5 [ns] 50 50 25 t ck @ cl max -1 (byte 18) [ns] 75 75 26 t ac sdram @ cl max -1 [ns] 50 50 27 t rpmin [ns] 3c 3c 28 t rrdmin [ns] 28 28 29 t rcdmin [ns] 3c 3c 30 t rasmin [ns] 28 28 31 module density per rank 40 40 32 t as, t cs [ns] 60 60
data sheet 22 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules spd contents 33 t ah, t ch [ns] 60 60 34 t ds [ns] 40 40 35 t dh [ns] 40 40 36 - 40 not used 00 00 41 t rcmin [ns] 37 37 42 t rfcmin [ns] 41 41 43 t ckmax [ns] 28 28 44 t dqsqmax [ns] 28 28 45 t qhsmax [ns] 50 50 46 not used 00 00 47 dimm pcb height 01 01 48 - 61 not used 00 00 62 spd revision 10 10 63 checksum of byte 0-62 0f 0f 64 jedec id code of infineon (1) c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 72 module manufacturer location xx xx 73 part number, char 1 36 36 74 part number, char 2 34 34 75 part number, char 3 44 44 76 part number, char 4 36 36 77 part number, char 5 34 34 78 part number, char 6 30 30 79 part number, char 7 32 32 80 part number, char 8 30 30 81 part number, char 9 47 48 82 part number, char 10 42 42 83 part number, char 11 44 44 84 part number, char 12 4c 4c 85 part number, char 13 35 35 86 part number, char 14 43 43 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 table 14 spd codes for hys64d64020hbdl?5?c and hys64d64020gbdl?5?c (cont?d) product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512 mb 512 mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?3033?1 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules spd contents data sheet 23 rev. 1.11, 2004-12 91 module revision code 0x 0x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number (1 - 4) xx xx 99 - 127 not used 00 00 table 15 spd codes for hys64d64020hbdl?6?c and hys64d64020gbdl?6?c product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?2533?0 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex 0 programmed spd bytes in e2prom 80 80 1 total number of bytes in e2prom 08 08 2 memory type ddr = 07h 07 07 3 # of row addresses 0d 0d 4 # number of column addresses 0a 0a 5 # of dimm ranks 02 02 6 data width (lsb) 40 40 7 data width (msb) 00 00 8 interface voltage levels 04 04 9 tck @ clmax (byte 18) [ns] 60 60 10 tac sdram @ clmax (byte 18) [ns] 70 70 11 dimm configuration type (non- / ecc) 00 00 12 refresh rate 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 00 15 tccd [cycles] 01 01 16 burst length supported 0e 0e 17 number of banks on sdram 04 04 18 cas latency 0c 0c 19 cs latency 01 01 table 14 spd codes for hys64d64020hbdl?5?c and hys64d64020gbdl?5?c (cont?d) product type hys64d64020gbdl?5?c hys64d64020hbdl?5?c organization 512 mb 512 mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc3200s?3033?1 jedec spd revision rev 1.0 rev 1.0 byte# description hex hex
data sheet 24 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules spd contents 20 we (write) latency 02 02 21 dimm attributes 20 20 22 component attributes c1 c1 23 t ck @ clmax -0.5 (byte 18) [ns] 75 75 24 t ac sdram @ clmax -0.5 [ns] 70 70 25 t ck @ clmax -1 (byte 18) [ns] 00 00 26 t ac sdram @ clmax -1 [ns] 00 00 27 t rpmin (ns) 48 48 28 t rrdmin [ns] 30 30 29 t rcdmin [ns] 48 48 30 t rasmin [ns] 2a 2a 31 module density per rank 40 40 32 t as , t cs [ns] 75 75 33 t ah , t ch [ns] 75 75 34 t ds [ns] 45 45 35 t dh [ns] 45 45 36 - 40 not used 00 00 41 t rcmin [ns] 3c 3c 42 t rfcmin [ns] 48 48 43 t ckmax [ns] 30 30 44 t dqsqmax [ns] 28 28 45 t qhsmax [ns] 50 50 46 - 61 not used 00 00 62 spd revision 00 00 63 checksum of byte 0-62 (lsb only) f8 f8 64 jedec id code for infineon c1 c1 65 jedec id code for infineon 00 00 66 jedec id code for infineon 00 00 67 jedec id code for infineon 00 00 68 jedec id code for infineon 00 00 69 jedec id code for infineon 00 00 70 jedec id code for infineon 00 00 71 jedec id code for infineon 00 00 72 module manufacturer location xx xx 73 part number, char 1 36 36 table 15 spd codes for hys64d64020hbdl?6?c and hys64d64020gbdl?6?c (cont?d) product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?2533?0 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules spd contents data sheet 25 rev. 1.11, 2004-12 74 part number, char 2 34 34 75 part number, char 3 44 44 76 part number, char 4 36 36 77 part number, char 5 34 34 78 part number, char 6 30 30 79 part number, char 7 32 32 80 part number, char 8 30 30 81 part number, char 9 47 48 82 part number, char 10 42 42 83 part number, char 11 44 44 84 part number, char 12 4c 4c 85 part number, char 13 36 36 86 part number, char 14 43 43 87 part number, char 15 20 20 88 part number, char 16 20 20 89 part number, char 17 20 20 90 part number, char 18 20 20 91 module revision code xx xx 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 - 98 module serial number xx xx 99 - 127 not used 00 00 table 15 spd codes for hys64d64020hbdl?6?c and hys64d64020gbdl?6?c (cont?d) product type hys64d64020gbdl?6?c hys64d64020hbdl?6?c organization 512mb 512mb 64 64 2 ranks ( 8) 2 ranks ( 8) label code pc2700s?2533?0 jedec spd revision rev. 0.0 rev. 0.0 byte# description hex hex
data sheet 26 rev. 1.11, 2004-12 hys64d64020[h/g] bdl?[5/6]?c small outline ddr sdram modules package outlines 5 package outlines figure 3 package outline so-dimm l-dim-200-22 0.1 63.6 67.6 31.75 4 0.1 11.4 1 47.4 0.1 (2.4) 0.1 18.45 1.8 0.1 0.1 (2.45) 0.1 0.1 1 0.1 1.5 (2.7) 4 6 0.1 0.1 20 2 min. 3.8 max. 0.1 1 0.1 5 (2.15) (2.45) 0.05 1.8 (2.15) 199 200 2 gld0957 3 detail of contacts 0.25 -0.1 8 0.45 0.03 0.6 0.1 2.55 burnished, no burr allowed
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